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PRELIMINARY
CYU01M16SCG MoBL3TM
16-Mbit (1M x 16) Pseudo Static RAM
Features
* Wide voltage range: 2.2V-3.6V * Access Time: 70 ns * Ultra-low active power -- Typical active current: 3 mA @ f = 1 MHz -- Typical active current: 18 mA @ f = fmax * Ultra low standby power * Automatic power-down when deselected * CMOS for optimum speed/power * Offered in a 48-ball BGA Package * Operating Temperature: -40C to +85C portable applications such as cellular telephones. The device can be put into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE1 HIGH or CE2 LOW), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE1 LOW and CE2 HIGH and WE LOW). To write to the device, take Chip Enable (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19). To read from the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. Refer to the truth table for a complete description of read and write modes.
Functional Description[1]
The CYU01M16SCG is a high-performance CMOS Pseudo Static RAM organized as 1M words by 16 bits that supports an asynchronous memory interface. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery LifeTM (MoBL(R)) in
Logic Block Diagram
DATA IN DRIVERS A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
ROW DECODER
1M x 16 RAM Array
SENSE AMPS
I/O0-I/O7 I/O8-I/O15
COLUMN DECODER BHE WE OE BLE
Pow -Down er Circuit
CE2 CE1 CE2 CE1
A7 A6 A5 A4 A3 A2 A1 A0
BHE BLE
Note: 1. For best-practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
Cypress Semiconductor Corporation Document #: 001-09739 Rev. **
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised August 7, 2006
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PRELIMINARY
Pin Configuration[2, 3]
48-Ball VFBGA
1 BLE I/O8 I/O9 VSS VCC I/O14 I/O15
A18
CYU01M16SCG MoBL3TM
2 OE BHE I/O10 I/O11
Top View 4 3 A0 A3 A5 A17 A1 A4 A6 A7 A16 A15 A13 A10
5 A2 CE1 I/O1 I/O3 I/O4 I/O5 WE A11
6 CE2 I/O0 I/O2 VCC VSS I/O6 I/O7 NC A B C D E F G H
I/O12 NC I/O13 A19 A8 A14 A12 A9
Product Portfolio[4]
Power Dissipation Product CYU01M16SCG Min. 2.2 VCC Range (V) Typ.[4] 3.0 Max. 3.6 70 Speed (ns) Operating ICC (mA) f = 1MHz Typ.[4] 3 Max. 5 f = fmax Typ.[4] 18 Max. 25 Standby ISB2 (A) Typ.[4] 55 Max. 70
Power-up Characteristics
The initialization sequence is shown in the figure below. Chip Select should be CE1 HIGH or CE2 LOW for at least 200 s after VCC has reached a stable value. No access must be attempted during this period of 200 s.
Stable Power VCC First Access Tpu CE
Parameter Tpu
Description Chip Enable Low After Stable VCC
Min. 200
Typ.
Max.
Unit s
Notes: 2. Ball H6 and E3 can be used to upgrade to a 32-Mbit and a 64-Mbit density, respectively. 3. NC "no connect" - not connected internally to the die. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC (typ) and TA = 25C. Tested initially and after design changes that may affect the parameters.
Document #: 001-09739 Rev. **
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PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential ..............................-0.3V to VCCMAX + 0.3V DC Voltage Applied to Outputs in High Z State[5, 6, 7] ........................-0.3V to VCCMAX + 0.3V
CYU01M16SCG MoBL3TM
DC Input Voltage[5, 6, 7] .................... -0.3V to VCCMAX + 0.3V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... > 200 mA Device CYU01M16SCG Range Industrial Operating Temperature (TA) -40C to +85C VCC 2.2V to 3.6V
DC Electrical Characteristics (Over the Operating Range)[5, 6, 7]
CYU01M16SCG-70 ns Parameter VCC VOH VOL VIH VIL IIX IOZ ICC Description Supply Voltage Output HIGH Voltage IOH = -0.1 mA VCC= 2.2V to 3.6V Output LOW Voltage IOL = 0.1 mA VCC= 2.2V to 3.6V Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current--CMOS Inputs Automatic CE Power-Down Current--CMOS Inputs VCC= 2.2V to 3.6V VCC= 2.2V to 3.6V GND < VIN < VCC GND < VOUT < VCC f = fMAX = 1/tRC VCC= VCCmax IOUT = 0 mA CMOS levels f = 1MHz ISB1 CE1 > VCC - 0.2V, CE2 < 0.2V, VIN > VCC - 0.2V, VIN < 0.2V, f = fMAX (Address and Data Only), f = 0 (OE, WE, BHE and BLE), VCC = 3.60V CE1 > VCC - 0.2V, CE2 < 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0, VCC=VCCMAX 0.8 * VCC -0.3 -1 -1 18 Test Conditions Min. 2.2 VCC - 0.2 0.2 VCC + 0.3V 0.2 * VCC +1 +1 25 Typ.[4] 3.0 Max. 3.6 Unit V V V V V A A mA
3 55
5 70
mA A
ISB2
55
70
A
Capacitance[8]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ) Max. 8 8 Unit pF pF
Thermal Resistance[8]
Parameter JA JC Description Test Conditions VFBGA 56 11 Unit C/W C/W Thermal Resistance (Junction to Ambient) Test conditions follow standard test methods and procedures for measuring thermal Thermal Resistance (Junction to Case) impedence, per EIA/JESD51
Notes: 5. VIL(MIN) = -0.5V for pulse durations less than 20 ns. 6. VIH(Max) = VCC + 0.5V for pulse durations less than 20 ns. 7. Overshoot and undershoot specifications are characterized and are not 100% tested. 8. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-09739 Rev. **
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PRELIMINARY
AC Test Loads and Waveforms
R1 VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 VCC GND 10% ALL INPUT PULSES 90% 90% 10%
CYU01M16SCG MoBL3TM
Rise Time = 1 V/ns Equivalent to:
Fall Time = 1 V/ns
THEVENIN EQUIVALENT RTH OUTPUT VTH Unit V
Parameters R1 R2 RTH VTH
3.0V (VCC) 26000 26000 13000 1.50
Switching Characteristics Over the Operating Range[9, 10, 11, 14, 15]
70 ns Parameter Read Cycle tRC[13] tCD tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tDBE tLZBE tHZBE Read Cycle Time Chip Deselect Time CE1 = HIGH or CE2 =LOW, BLE/BHE High Pulse Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low CE LOW to Low Z[10, 11, 12] Z[10, 11, 12] 10 25 70 5 25 Z[10, 11, 12] 5 25 OE HIGH to High 5 70 35 70 15 70 40000 ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Unit
CE HIGH to High Z[10, 11, 12] BLE/BHE LOW to Data Valid BLE/BHE LOW to Low Z
[10, 11, 12] [10, 11, 12]
BLE/BHE HIGH to High Z
Notes: 9. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of VCC(typ.)/2, input pulse levels of 0V to VCC, and output loading of the specified IOL/IOH as shown in the "AC Test Loads and Waveforms" section. 10. At any given temperature and voltage conditions tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. All low-Z parameters will be measured with a load capacitance of 30 pF (3V). 11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 12. High-Z and Low-Z parameters are characterized and are not 100% tested. 13. If invalid address signals shorter than min.tRC are continuously repeated for 40 s, the device needs a normal read timing (tRC) or needs to enter standby state at least once in every 40 s. 14. In order to achieve 70-ns performance, the read access must be Chip Enable (CE1 or CE2) controlled. That is, the addresses must be stable prior to Chip Enable going active.
Document #: 001-09739 Rev. **
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PRELIMINARY
Switching Characteristics Over the Operating Range[9, 10, 11, 14, 15] (continued)
70 ns Parameter Write Cycle tWC tSCE tAW tCD tHA tSA tPWE tBW tSD tHD tHZWE tLZWE
[15]
CYU01M16SCG MoBL3TM
Description Write Cycle Time CE LOW to Write End Address Set-Up to Write End Chip Deselect Time CE1 = HIGH or CE2 =LOW, BLE/BHE High Pulse Time Address Hold from Write End Address Set-Up to Write Start WE Pulse Width BLE/BHE LOW to Write End Data Set-Up to Write End Data Hold from Write End WE LOW to High-Z[10, 11, 12] WE HIGH to Low-Z[10, 11, 12]
Min. 70 60 60 15 0 0 50 60 25 0
Max. 40000
Unit ns ns ns ns ns ns ns ns ns ns
25 10
ns ns
Note: 15. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL or CE2 = VIH, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
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PRELIMINARY
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)[17, 18] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA
CYU01M16SCG MoBL3TM
DATA VALID
Read Cycle 2 (OE Controlled)[16, 18, 19]
ADDRESS tRC
CE1
tCD
tHZCE
CE2
tACE
BHE/BLE
tLZBE
OE
tDBE
tHZBE
IMPEDANCE
DATA OUT VCC SUPPLY CURRENT
tLZOE HIGH IMPEDANCE tLZCE
tDOE DATA VALID
tHZOE HIGH
50%
50%
ICC ISB
Notes: 16. Whenever CE1 = HIGH or CE2 = LOW, BHE/BLE are taken inactive, they must remain inactive for a minimum of 5 ns. 17. Device is continuously selected. OE = CE1 = VIL and CE2 = VIH. 18. WE is HIGH for Read Cycle. 19. CE is the Logical AND of CE1 and CE2.
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PRELIMINARY
Switching Waveforms (continued)
Write Cycle 1 (WE Controlled)[15, 12, 16, 19, 20, 21]
CYU01M16SCG MoBL3TM
t WC
ADDRESS tSCE
CE1
tCD
CE2
tAW tSA
WE
tHA tPWE
BHE/BLE
tBW
OE
tSD DATA I/O
DON'T CARE
tHD
VALID DATA tHZOE
Notes: 20. Data I/O is high-impedance if OE > VIH. 21. During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
Document #: 001-09739 Rev. **
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PRELIMINARY
Switching Waveforms (continued)
Write Cycle 2 (CE1 or CE2 Controlled)[15, 12, 16, 20, 21] tWC ADDRESS tSCE CE1 CE2 tSA tAW tPWE tHA
CYU01M16SCG MoBL3TM
WE tBW
BHE/BLE
OE tSD DATA I/O
DON'T CARE
tHD
VALID DATA tHZOE
Write Cycle 3 (WE Controlled, OE LOW)[16, 21]
tWC ADDRESS tSCE
CE1
CE2
BHE/BLE
tBW tAW tSA tPWE
t HD
tHA
WE
tSD DATAI/O
DON'T CARE
VALID DATA tHZWE tLZWE
Document #: 001-09739 Rev. **
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PRELIMINARY
Switching Waveforms (continued)
Write Cycle 4 (BHE/BLE Controlled, OE LOW)[15, 16, 20, 21]
CYU01M16SCG MoBL3TM
tWC ADDRESS
CE1 CE2 tSCE tAW BHE/BLE tSA WE tPWE tSD DATA I/O
DON'T CARE
tHA tBW
tHD
VALID DATA
Truth Table[22]
CE1 H X X L L L L L L L L L CE2 X L X H H H H H H H H H WE X X X H H H H H H L L L OE X X X L L L H H H X X X BHE X X H L H L L H L L H L BLE X X H L L H L L H L L H Inputs/Outputs High Z High Z High Z Data Out (I/O0-I/O15) Data Out (I/O0-I/O7); I/O8-I/O15 in High Z Data Out (I/O8-I/O15); I/O0-I/O7 in High Z High Z High Z High Z Data In (I/O0-I/O15) Data In (I/O0-I/O7); I/O8-I/O15 in High Z Data In (I/O8-I/O15); I/O0 -I/O7 in High Z Mode Deselect/Power-down Deselect/Power-down Deselect/Power-down Read Read Read Output Disabled Output Disabled Output Disabled Write (Upper Byte and Lower Byte) Write (Lower Byte Only) Write (Upper Byte Only) Power Standby (ISB) Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Note: 22. H = Logic HIGH, L = Logic LOW, X = Don't Care.
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PRELIMINARY
Ordering Information
Speed (ns) 70 Ordering Code CYU01M16SCG-70BVXI Package Diagram 51-85150 Package Type
CYU01M16SCG MoBL3TM
Operating Range Industrial
48-ball Fine Pitch VBGA (6 mm x 8 mm x 1 mm) (Pb-Free)
Package Diagram
48-ball VFBGA (6 x 8 x 1 mm) (51-85150)
BOTTOM VIEW A1 CORNER O0.05 M C O0.25 M C A B A1 CORNER O0.300.05(48X) 1 2 3 4 5 6 6 5 4 3 2 1
TOP VIEW
A B C 8.000.10 8.000.10 0.75 5.25 D E F G H
A B C D E 2.625 F G H
A B 6.000.10
A
1.875 0.75 3.75 B 6.000.10
0.55 MAX.
0.25 C
0.15(4X) 0.210.05 0.10 C
51-85150-*D
SEATING PLANE 0.26 MAX. C 1.00 MAX
MoBL is a registered trademark and MoBL3 and More Battery Life are trademarks of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 001-09739 Rev. **
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(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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PRELIMINARY
Document History Page
Document Title: CYU01M16SCG MoBL3TM 16-Mbit (1M x 16) Pseudo Static RAM Document Number: 001-09739 REV. ** ECN NO. Issue Date 497844 See ECN Orig. of Change NXR New Data sheet
CYU01M16SCG MoBL3TM
Description of Change
Document #: 001-09739 Rev. **
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